Four Ways to Enhance ESD Protection After Your Design Flunks Its ESD Test

Authored by: Chad Marak Jim Colby Silicon Protection Arrays Littelfuse Inc. Chicago, Ill. Edited by Robert Repas Key points: •ESD protectors with low dynamic resistance won’t necessarily protect circuits. •Most damage is caused within the first nanosecond of an ESD event. •The ESD protector should set as close as possible to the point of current entry, not to the device being protected. Resources: Littelfuse Inc., www.littelfuse.com Dissipating static safely, machinedesign.com/article/dissipating-static-safely-0705 Top tips on squelching electrical noise, machinedesign.com/article/top-tips-on-squelching-electrical-noise-0619

The generally accepted main goal of electrostatic-discharge (ESD) protection is to provide a low-resistance shunt path to ground (GND) for unwanted voltage spikes. A key to how well such measures serve their purpose is its dynamic-resistance figure used in the selection process. Fortunately, there are well-known ways to calculate the effective dynamic-resistance that protection devices, such as polymeric ESD suppressors or silicon-diode arrays, exhibit during an ESD transient.

Logic dictates that the device with the lowest dynamic resistance should give the best chance of dissipating spikes. But sometimes it doesn’t. All is not lost, however, as several techniques help boost the level of ESD protection.

The challenge
The standard ESD pulse shape is defined by IEC61000-4-2. It specifies an initial current spike with a peak voltage of 2,000 to 8,000 V and a rise time of 0.7 to 1.0 nsec. Current level is rated at 3.75 A/kV at the peak voltage, or 30 A for an 8-kV voltage test. Current levels at 30 and 60 nsec are also specified at 2 A/kV and 1 A/kV, respectively.

This presents a special challenge to many modern electronic products built with state-of-the-art chipsets that use construction technologies well below 130 nm. These technologies poorly tolerate any dc voltage over 3.3 V, so an ESD pulse can be catastrophic for such a device. Furthermore, chipmakers have reduced onboard or on-chip ESD protection to 500 V, well below the typical field requirement of 8 kV.

Board designers not only need external ESD protection, but also need to make sure it’s robust enough to protect small-geometry chipsets. Just placing an 8-kV rated ESD protection device on the data lines or I/O pins being protected does not guarantee the chip set itself will pass an 8 kV in-system test.

Board layout and device location are crucial for effective protection from ESD. To that end, the designer must understand the effects that parasitic inductances have at the board level. For example, an 8-kV ESD strike at the test specification of 30 A through a printed-circuit board (PCB) trace with just 1-nH inductance generates a 30-V spike on that trace. This voltage is calculated using the equation:

V_{L, parasitic} = L_parasitic × di/dt

where L_parasitic is the parasitic inductance of the trace and V_{L, parasitic} is the voltage developed across it with the change in current over time, di/dt.

In looking at a typical circuit-board layout, the input trace circuit can be divided into four separate areas: the trace from the input to the junction of the ESD device (L_port), the trace from the ESD junction to the input of the IC (L_IC), the trace from the junction of the ESD device to the device itself (L_ESD), and the trace from the ESD device to ground (L_GND). These four parasitic inductances, L_ESD, L_GND, L_IC, and L_port, must be considered when deciding on the placement of the ESD device. L_ESD and L_GND tend to raise the clamping voltage (V_IC) while L_IC and L_port work to the designer’s advantage to lowerV_IC.

Shorten traces to lower L_ESD and L_GND
Sometimes a board’s layout prevents an ESD device being placed directly atop the PCB trace. Reasons vary, but placing an ESD component even 1 cm away from the data line being protected can ultimately translate into tens of volts on the device. The same is true for ground (GND) buses. In some designs the ESD device GND must pass through multiple vias and may even take a circuitous path to reach the GND plane. Both of these inductances create voltage spikes in addition to the voltage created by the ESD current flowing through the ESD device given by V_ESD = I_peak × R_dynamic, where VESD is the voltage drop across the ESD device, I_peak is the peak current of the electrostatic event, and R_dynamic is the resistance of the ESD device as it conducts.

The following simplified examples show how L_ESD and L_GND affect V_IC. Common PCB manufacturing processes give approximately 3 nH/cm for typical microstrip traces assuming certain widths, thicknesses, and dielectric constants. With that in mind, assume an 8kV ESD pulse is applied to the input of the I/O pin. The ESD device has a 1-Ω dynamic resistance. The first layout assumes both L_ESD and L_GND equal 1.5 nH (0.5-cm spacing):

V_IC = (L_ESD + L_GND) × di/dt + I_peak × R_dynamic

V_IC = (1.5 nH + 1.5 nH) × 30 A/1 nsec + 30 A × 1.0 Ω
= 120 V

The second layout doubles the length of the traces, so each become 1-cm long for 3-nH each:

V_IC = (3 nH + 3 nH) × 30 A/1 nsec + 30 A × 1.0 Ω
= 210 V

This example shows that lengthening the ESD protector trace from 0.5 to 1 cm increasesV_IC by 75%! So the rule is to keep the traces connecting the ESD protector as short as possible.

Shrink the ratio of L_port to L_IC
Often datasheets for ESD protectors recommend putting the device as close as possible to the point of ESD entry. Manufacturers do this so the ratio of L_port to L_IC is as small as possible (L_IC >> L_port). The inductance of L_port will not necessarily affect the overall ESD performance but the inductance of L_IC most certainly will.